MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 6 XGATE (S12XGATEV2)
CSL
Operation
C
Logical Shift Left with Carry
CSL
C
C
n
bits
n
RD
C
C
n
= RS or IMM4
Shifts the bits in register RD
n
positions to the left. The lower
n
bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for
n
> 0.
n
can range from 0 to 16.
In immediate address mode,
n
is determined by the operand IMM4.
n
is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode,
n
is determined by the content of RS.
n
is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
∆
N:
Z:
V:
C:
Z
∆
V
∆
C
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
old
^ RD[15]
new
Set if
n
> 0 and RD[16-n] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
CSL RD, #IMM4
CSL RD, RS
Address
Mode
IMM4
DYA
0
0
0
0
0
0
0
0
1
1
Machine Code
RD
RD
IMM4
RS
1
1
0
0
0
1
1
0
0
Cycles
P
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
255