MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
External Signal Description
This section lists and describes the signals that do connect off-chip.
24.0.3
Signal Properties
Table 24-1
shows all the pins and their functions that are controlled by the PIM.
Refer to
Section ,
“Functional Description”
for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 24-1. Pin Functions and Priorities (Sheet 1 of 5)
Port
—
Pin Name
BKGD
Pin Function
and Priority
MODC
1
BKGD
A
B
PA[7:0]
PB[7:0]
GPIO
GPIO
XCLKS
1
PE[7]
ECLKX2
GPIO
PE[6:5]
GPIO
ECLK
E
PE[4]
GPIO
PE[3:2]
PE[1]
GPIO
XIRQ
PE[0]
GPIO
PK[7]
K
PK[5:0]
T
PT[7:0]
GPIO
I/O
General-purpose I/O
GPIO
IOC[7:0]
I/O
I/O
General-purpose I/O
Enhanced Capture Timer Channels 7–0 input/output
GPIO
GPIO
I/O
I/O
General-purpose I/O
General-purpose I/O
GPIO
I/O
I
General-purpose I/O
Non-maskable level-sensitive interrupt input
GPIO
IRQ
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I
I
I/O
I/O
O
Description
MODC input during RESET
S12X_BDM communication pin
General-purpose I/O
General-purpose I/O
External clock selection input during RESET
Free-running clock output at Core Clock rate (ECLK x 2)
General-purpose I/O
General-purpose I/O
Free-running clock output at the Bus Clock rate or
programmable divided in normal modes
General-purpose I/O
General-purpose I/O
Maskable level- or falling edge-sensitive interrupt input
GPIO
GPIO
Pin Function
after Reset
BKGD
MC9S12XDP512 Data Sheet, Rev. 2.21
978
Freescale Semiconductor
