MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
9.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
IBAD
R
W
IBFD
R
W
IBCR
R
W
IBSR
R
W
IBDR
R
W
D7
D6
D5
Bit 7
ADR7
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
1
ADR1
Bit 0
0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
0
IBC1
0
IBC0
IBEN
TCF
IBIE
IAAS
MS/SL
IBB
Tx/Rx
TXAK
0
RSTA
SRW
IBIF
IBSWAI
RXAK
IBAL
D4
D3
D2
D1
D0
= Unimplemented or Reserved
Figure 9-2. IIC Register Summary
9.3.2.1
IIC Address Register (IBAD)
7
6
5
4
3
2
1
0
R
ADR7
W
Reset
0
0
0
0
0
0
0
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
0
0
= Unimplemented or Reserved
Figure 9-3. IIC Bus Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Table 9-1. IBAD Field Descriptions
Field
7:1
ADR[7:1]
0
Reserved
Description
Slave Address
— Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
MC9S12XDP512 Data Sheet, Rev. 2.21
398
Freescale Semiconductor