MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 6 XGATE (S12XGATEV2)
BFINSI
Operation
!RS1[w:0]
⇒
RD[w+o:o];
w
= (RS2[7:4])
o
= (RS2[3:0])
Bit Field Insert and Invert
BFINSI
Extracts
w+1
bits from register RS1 starting at position 0, inverts them and writes into register RD starting
at position
o.
The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using
R0 as a RS1, this command can be used to set bits.
15
7
W4
15
3
4
3
O4
0
RS1
Inverted Bit Field Insert
15
5
2
0
RD
0
RS2
W4=3, O4=2
CCR Effects
N
∆
N:
Z:
V:
C:
Z
∆
V
0
C
—
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BFINSI RD, RS1, RS2
Address
Mode
TRI
0
1
1
1
0
Machine Code
RD
RS1
RS2
1
1
Cycles
P
MC9S12XDP512 Data Sheet, Rev. 2.21
230
Freescale Semiconductor