MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 18 Memory Mapping Control (S12XMMCV3)
Address
0x011D
Register
Name
RAMXGU
R
W
Bit 7
1
6
XGU6
5
XGU5
4
XGU4
3
XGU3
2
XGU2
1
XGU1
Bit 0
XGU0
0x011E
RAMSHL
R
W
1
SHL6
SHL5
SHL4
SHL3
SHL2
SHL1
SHL0
0x011F
RAMSHU
R
W
1
SHU6
SHU5
SHU4
SHU3
SHU2
SHU1
SHU0
= Unimplemented or Reserved
Figure 18-2. MMC Register Summary
18.3.2
18.3.2.1
Register Descriptions
MMC Control Register (MMCCTL0)
Address: 0x000A PRR
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
CS3E
0
CS2E
0
CS1E
0
CS0E
ROMON
1
1. ROMON is bit[0] of the register MMCTL1 (see
Figure 18-10)
= Unimplemented or Reserved
Figure 18-3. MMC Control Register (MMCCTL0)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 18-4. Chip Selects Function Activity
Chip Modes
Register Bit
NS
CS3E, CS2E, CS1E, CS0E
1
2
SS
Disabled
NX
Enabled
2
ES
Disabled
EX
Enabled
ST
Enabled
Disabled
1
Disabled: feature always inactive.
Enabled: activity is controlled by the appropriate register bit value.
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
657