MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 21 External Bus Interface (S12XEBIV2)
Table 21-17. Access in Normal Expanded Mode
DATA[15:8]
Access
Word write of data on DATA[15:0] at an even and even+1 address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word read of data on DATA[15:0] at an even and even+1 address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Indicates No Access
Unimplemented
RE WE UDS LDS
I/O data(addr) I/O data(addr)
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
Out data(even) Out
In
In
In
In
In
In
In
x
data(even)
x
data(even)
x
x
x
Out
In
In
In
In
In
In
In
Out data(even)
data(odd)
data(odd)
x
data(odd)
data(odd)
x
x
x
x
DATA[7:0]
21.4.5.2
Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, R/W, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in
Table 21-18.
Table 21-18. Access in Emulation Modes and Special Test Mode
DATA[15:8]
Access
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
R/W LSTRB ADDR0
I/O
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Out
In
Out
data(addr)
data(even)
x
data(odd)
I/O
Out
Out
In
data(addr)
data(odd)
data(odd)
x
data(odd)
data(even+1)
data(odd)
x
data(odd)
DATA[7:0]
Out data(odd+1) Out
In
In
In
In
data(even)
x
data(even)
data(odd+1)
In
In
In
In
MC9S12XDP512 Data Sheet, Rev. 2.21
800
Freescale Semiconductor
