MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.3
ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
7
6
5
4
3
2
1
0
R
W
Reset
ADPU
0
AFFC
0
AWAI
0
ETRIGLE
0
ETRIGP
0
ETRIGE
0
ASCIE
0
ASCIF
0
= Unimplemented or Reserved
Figure 5-5. ATD Control Register 2 (ATDCTL2)
Read: Anytime
Write: Anytime
Table 5-5. ATDCTL2 Field Descriptions
Field
7
ADPU
Description
ATD Power Up
— This bit provides on/off control over the ATD block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
clear the associate CCF flag).
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will
cause the associate CCF flag to clear automatically.
ATD Power Down in Wait Mode
— When entering wait mode this bit provides on/off control over the ATD block
allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires
a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during wait mode
After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of
this conversion should be ignored.
External Trigger Level/Edge Control
— This bit controls the sensitivity of the external trigger signal. See
Table 5-6
for details.
External Trigger Polarity
— This bit controls the polarity of the external trigger signal. See
Table 5-6
for
External Trigger Mode Enable
— This bit enables the external trigger on one of the AD channels or one of
the ETRIG3–0 inputs as described in
Table 5-4.
If external trigger source is one of the AD channels, the digital
input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions
processes with external events.
0 Disable external trigger
1 Enable external trigger
Note:
If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel
have no meaning while external trigger mode is enabled.
6
AFFC
5
AWAI
4
ETRIGLE
3
ETRIGP
2
ETRIGE
MC9S12XDP512 Data Sheet, Rev. 2.21
168
Freescale Semiconductor
