MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 17 Memory Mapping Control (S12XMMCV2)
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 17-4. MMCCTL0 Field Descriptions
Field
3–0
CS[3:0]E
Description
Chip Select Enables
— Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0
outputs which are asserted during accesses to specific external addresses. The associated global address
ranges are shown in
Table 1-6
and
Table 1-21
and
Figure 1-23.
Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test
mode. The function disabled in all other operating modes.
0 Chip select is disabled
1 Chip select is enabled
Table 17-5. Chip Select Signals
Global Address Range
0x00_0800–0x0F_FFFF
0x10_0000–0x1F_FFFF
0x20_0000–0x3F_FFFF
0x40_0000–0x7F_FFFF
1
Asserted Signal
CS3
CS2
CS1
CS0
1
When the internal NVM is enabled (see ROMON in
Section 1.3.2.5, “MMC Control
Register (MMCCTL1)”)
the CS0 is not asserted in the space occupied by this on-chip
memory block.
MC9S12XDP512 Data Sheet, Rev. 2.21
618
Freescale Semiconductor