MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
Table 5-5. ATDCTL2 Field Descriptions (continued)
Field
1
ASCIE
0
ASCIF
Description
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
ATD Sequence Complete Interrupt Flag
— If ASCIE = 1 the ASCIF flag equals the SCF flag (see
Section 5.3.2.7, “ATD Status Register 0 (ATDSTAT0)”),
else ASCIF reads zero. Writes have no effect.
0 No ATD interrupt occurred
Table 5-6. External Trigger Configurations
ETRIGLE
0
0
1
1
ETRIGP
0
1
0
1
External Trigger Sensitivity
Falling edge
Rising edge
Low level
High level
5.3.2.4
ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in freeze
mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
7
6
5
4
3
2
1
0
R
W
Reset
0
0
S8C
0
S4C
0
S2C
0
S1C
0
FIFO
0
FRZ1
0
FRZ0
0
= Unimplemented or Reserved
Figure 5-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime
Write: Anytime
Table 5-7. ATDCTL3 Field Descriptions
Field
6–3
S8C, S4C,
S2C, S1C
Description
Conversion Sequence Length
— These bits control the number of conversions per sequence.
Table 5-8
shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
169