MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Table 24-4. PORTA Field Descriptions
Field
7–0
PA[7:0]
Description
Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
24.0.5.2
7
Port B Data Register (PORTB)
6
5
4
3
2
1
0
R
PB7
W
Reset
0
0
0
0
0
0
0
0
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Figure 24-4. Port B Data Register (PORTB)
Read: Anytime.
Write: Anytime.
Table 24-5. PORTB Field Descriptions
Field
7–0
PB[7:0]
Description
Port B
— Port B pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O
pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state
is read.
24.0.5.3
7
Port A Data Direction Register (DDRA)
6
5
4
3
2
1
0
R
DDRA7
W
Reset
0
0
0
0
0
0
0
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Figure 24-5. Port A Data Direction Register (DDRA)
Read: Anytime.
Write: Anytime.
Table 24-6. DDRA Field Descriptions
Field
7–0
DDRA[7:0]
Description
Data Direction Port A — This register controls the data direction for port A. DDRA determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note:
Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTA after changing the DDRA register.
