Home > Data Sheet > MC9S12XDP512CFU

MC9S12XDP512CFU

Model	MC9S12XDP512CFU
Description	16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80
PDF file	Total 1348 pages (File size: 8M)
Chip Manufacturer	PHILIPS

Download (8M)

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

22.4

Functional Description

Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an

output from the external bus interface module or a peripheral module or an input to the external bus

interface module or a peripheral module.

A set of configuration registers is common to all ports with exceptions in the expanded bus interface and

ATD ports (Table

22-67).

All registers can be written at any time; however a specific configuration might

not become active.

Example: Selecting a pull-up device

This device does not become active while the port is used as a push-pull output.

Table 22-67. Register Availability per Port

Port

AD0

AD1

Data

yes

Data

Direction

yes

Input

—

yes

—

Reduced

Drive

yes

Pull

Enable

yes

Polarity

Select

—

Wired-OR

Mode

—

yes

—

Interrupt

Enable

—

yes

—

Interrupt

Flag

—

yes

—

yes

—

yes

—

Each cell represents one register with individual conﬁguration bits

22.4.1

22.4.1.1

Registers

Data Register

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output. When

reading this address, the buffered state of the pin is returned if the associated data direction register bit is

set to “0”.

If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This

is independent of any other configuration (Figure

22-76).

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

881

prev next