MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 2 Clocks and Reset Generator (S12CRGV6)
Table 2-13. Outcome of Clock Loss in Pseudo Stop Mode
CME
0
1
SCME
X
0
SCMIE
X
X
Clock failure -->
No action, clock loss not detected.
Clock failure -->
CRG performs Clock Monitor Reset immediately
Clock Monitor failure -->
Scenario 1: OSCCLK
recovers
prior to exiting pseudo stop mode.
– MCU remains in pseudo stop mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
– SCM deactivated,
– PLL disabled,
– VREG disabled.
– MCU remains in pseudo stop mode.
Some
time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit pseudo stop mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
or an External Reset is applied.
– Exit pseudo stop mode using OSCCLK as system clock,
– Start reset sequence.
Scenario 2: OSCCLK
does not recover
prior to exiting pseudo stop mode.
– MCU remains in pseudo stop mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag,
– Keep performing clock quality checks (could continue infinitely) while
in pseudo stop mode.
Some
time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit pseudo stop mode in SCM using PLL clock (f
SCM
) as system clock
– Continue to perform additional clock quality checks until OSCCLK is o.k. again.
or an External RESET is applied.
– Exit pseudo stop mode in SCM using PLL clock (f
SCM
) as system clock
– Start reset sequence,
– Continue to perform additional clock quality checks until OSCCLK is o.k.again.
Clock failure -->
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– SCMIF set.
SCMIF generates self clock mode wakeup interrupt.
– Exit pseudo stop mode in SCM using PLL clock (f
SCM
) as system clock,
– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
CRG Actions
1
1
0
1
1
1
MC9S12XDP512 Data Sheet, Rev. 2.21
110
Freescale Semiconductor
