MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 10-7. Time Segment 2 Values
TSEG22
0
0
:
1
1
1
TSEG21
0
0
:
1
1
TSEG20
0
1
:
0
1
Time Segment 2
1 Tq clock cycle
1
2 Tq clock cycles
:
7 Tq clock cycles
8 Tq clock cycles
This setting is not valid. Please refer to
Table 10-35
for valid settings.
Table 10-8. Time Segment 1 Values
TSEG13
0
0
0
0
:
1
1
1
TSEG12
0
0
0
0
:
1
1
TSEG11
0
0
1
1
:
1
1
TSEG10
0
1
0
1
:
0
1
Time segment 1
1 Tq clock cycle
1
2 Tq clock cycles
1
3 Tq clock cycles
1
4 Tq clock cycles
:
15 Tq clock cycles
16 Tq clock cycles
This setting is not valid. Please refer to
Table 10-35
for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
Table 10-7
and
Table 10-8).
Eqn. 10-1
(
Prescaler value
)
Bit Time = -----------------------------------------------------
• (
1 + TimeSegment1 + TimeSegment2
)
-
f CANCLK
10.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
7
6
5
4
3
2
1
0
R
WUPIF
W
Reset:
0
0
CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0
OVRIF
RXF
0
0
0
0
0
0
= Unimplemented
Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)
MC9S12XDP512 Data Sheet, Rev. 2.21
430
Freescale Semiconductor