MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 18 Memory Mapping Control (S12XMMCV3)
;automatically select direct mode.
18.3.2.5
MMC Control Register (MMCCTL1)
Address: 0x0013 PRR
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
EROMON
EROMCTL
ROMHM
0
ROMON
ROMCTL
= Unimplemented or Reserved
Figure 18-10. MMC Control Register (MMCCTL1)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.Write: Refer to each bit description. In emulation modes write
operations will also be directed to the external bus.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 18-10. MMCCTL1 Field Descriptions
Field
2
EROMON
Description
Enables emulated Flash or ROM memory in the memory map
Write: Never
This bit is used in some modes to define the placement of the Emulated Flash or ROM (Refer to
Table 18-11)
0 Disables the emulated Flash or ROM in the memory map.
1 Enables the emulated Flash or ROM in the memory map.
FLASH or ROM only in higher Half of Memory Map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
0x4000–0x7FFF will be mapped to 0x7F_4000-0x7F_7FFF in the global memory space.
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Flash or ROM can still be accessed through the program page window. Accesses to 0x4000–0x7FFF will be
mapped to 0x14_4000-0x14_7FFF in the global memory space (external access).
Enable FLASH or ROM in the memory map
Write: Once in normal and emulation modes and anytime in special modes.
This bit is used in some modes to define the placement of the ROM (Refer to
Table 18-11)
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the memory map.
1
ROMHM
0
ROMON
EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for
XGATE). Both local and global memory maps are affected.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
663
