MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 20 S12X Debug (S12XDBGV3) Module
Address
0x002A
Name
DBGXAM
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 15
6
14
5
13
4
12
3
11
2
10
1
9
Bit 0
Bit 8
0x002B
DBGXAL
Bit 7
6
5
4
3
2
1
Bit 0
0x002C
DBGXDH
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
DBGXDL
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
DBGXDHM
Bit 15
14
13
12
11
10
9
Bit 8
0x002F
1
2
R
Bit 7
6
5
4
3
2
W
This represents the contents if the Comparator A or C control register is blended into this address.
This represents the contents if the Comparator B or D control register is blended into this address
DBGXDLM
1
Bit 0
Figure 20-2. Quick Reference to S12XDBG Registers
20.3.2
Register Descriptions
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the
S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
20.3.2.1
Debug Control Register 1 (DBGC1)
Address: 0x0020
7
6
5
4
3
2
1
0
R
W
Reset
ARM
0
0
TRIG
0
XGSBPE
0
BDM
0
0
DBGBRK
0
0
COMRV
0
Figure 20-3. Debug Control Register (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime, bit 6 can be written anytime but always reads back as 0.
Bits 5:2 anytime S12XDBG is not armed.
NOTE
When disarming the S12XDBG by clearing ARM with software, the
contents of bits[5:2] are not affected by the write, since up until the write
operation, ARM = 1 preventing these bits from being written. These bits
must be cleared using a second write if required.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
749
