MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 21 External Bus Interface (S12XEBIV2)
21.4
Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
21.4.1
Operating Modes and External Bus Properties
Table 21-7. Summary of Functions
Single-Chip Modes
Expanded Modes
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
A summary of the external bus interface functions for each operating mode is shown in
Table 21-7.
Properties
(if Enabled)
Normal
Single-Chip
Special
Single-Chip
Timing Properties
PRR access
1
2 cycles
read internal
write internal
—
—
2 cycles
read internal
write internal
—
—
2 cycles
read internal
write internal
—
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
3
—
Signal Properties
Bus signals
—
—
ADDR[22:1]
DATA[15:0]
ADDR[22:20]/A ADDR[22:20]/A
CC[2:0]
CC[2:0]
ADDR[19:16]/ ADDR[19:16]/
IQSTAT[3:0]
IQSTAT[3:0]
ADDR[15:0]/
ADDR[15:0]/
IVD[15:0]
IVD[15:0]
DATA[15:0]
DATA[15:0]
ADDR0
LSTRB
R/W
—
DATA[15:0]
EWAIT
ADDR0
LSTRB
R/W
EWAIT
DATA[15:0]
EWAIT
ADDR[22:0]
DATA[15:0]
2 cycles
read external
write int & ext
1 cycle
1 cycle
2 cycles
read external
write int & ext
1 cycle
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
3
1 cycle
2 cycles
read internal
write internal
1 cycle
1 cycle
Internal access
visible externally
External
address access
and
unimplemented area
access
2
Flash area
address access
4
—
—
1 cycle
1 cycle
Data select signals
(if 16-bit data bus)
Data direction signals
External wait
feature
Reduced input
threshold enabled on
1
2
3
4
—
—
—
—
—
—
—
—
UDS
LDS
RE
WE
EWAIT
Refer to
Table 21-3
ADDR0
LSTRB
R/W
—
Refer to
Table 21-3
Incl. S12X_EBI registers
Refer to S12X_MMC section.
If EWAITE = 1, the minimum number of external bus cycles is 3.
Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
MC9S12XDP512 Data Sheet, Rev. 2.21
794
Freescale Semiconductor
