S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
Offset Module Base + 0x0006
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
7
6
5
4
3
2
1
0
R
CCIF
W
Reset
1
0
ACCERR
0
0
FPVIOL
0
MGBUSY
RSVD
MGSTAT[1:0]
0
0
0
(1)
0
1
= Unimplemented or Reserved
Figure 27-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
Section 27.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Table 27-17. FSTAT Field Descriptions
Field
7
CCIF
Description
Command Complete Interrupt Flag
— The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag
— The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
Section 27.4.1.2)
or issuing an illegal Flash
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag
—The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag
— The MGBUSY flag reflects the active state of the Memory Controller
.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
Reserved Bit
— This bit is reserved and always reads 0
.
5
ACCERR
4
FPVIOL
3
MGBUSY
2
RSVD
1–0
Memory Controller Command Completion Status Flag
— One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See
Section 27.4.2,
“Flash Command Description,”
and
Section 27.6, “Initialization”
for details.
27.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
1033
