S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 4 Memory Protection Unit (S12XMPUV1)
Field
6
NEX
Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
No-Execute bit
— The NEX bit prevents the described memory range from being used as code memory. If this
bit is set every Op-code fetch in this memory range causes an access violation.
3–0
Memory range upper boundary address bits
— The HIGH_ADDR[22:19] bits represent bits [22:19] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
22:19]
4.3.1.10
MPU Descriptor Register 4 (MPUDESC4)
7
6
5
4
3
2
1
0
Address: Module Base + 0x000A
R
W
Reset
1
1
1
HIGH_ADDR[18:11]
1
1
1
1
1
Figure 4-12. MPU Descriptor Register 4 (MPUDESC4)
Read: Anytime
Write: Anytime
Table 4-12. MPUDESC4 Field Descriptions
Field
Description
7–0
Memory range upper boundary address bits
— The HIGH_ADDR[18:11] bits represent bits [18:11] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
18:11]
4.3.1.11
MPU Descriptor Register 5 (MPUDESC5)
7
6
5
4
3
2
1
0
Address: Module Base + 0x000B
R
W
Reset
1
1
1
HIGH_ADDR[10:3]
1
1
1
1
1
Figure 4-13. MPU Descriptor Register 5 (MPUDESC5)
Read: Anytime
Write: Anytime
Table 4-13. MPUDESC5 Field Descriptions
Field
Description
7–0
Memory range upper boundary address bits
— The HIGH_ADDR[10:3] bits represent bits [10:3] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
10:3]
MC9S12XE-Family Reference Manual , Rev. 1.19
236
Freescale Semiconductor
