S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 7 Background Debug Module (S12XBDMV2)
7.3
7.3.1
Memory Map and Register Definition
Module Memory Map
Table 7-2. BDM Memory Map
Global Address
0x7FFF00–0x7FFF0B
0x7FFF0C–0x7FFF0E
0x7FFF0F
0x7FFF10–0x7FFFFF
Module
BDM registers
BDM firmware ROM
Family ID (part of BDM firmware ROM)
BDM firmware ROM
Size
(Bytes)
12
3
1
240
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Table 7-2
shows the BDM memory map when BDM is active.
7.3.2
Register Descriptions
A summary of the registers associated with the BDM is shown in
Figure 7-2.
Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global
Address
0x7FFF00
Register
Name
Reserved
R
W
0x7FFF01
BDMSTS
R
W
0x7FFF02
Reserved
R
W
0x7FFF03
Reserved
R
W
0x7FFF04
Reserved
R
W
0x7FFF05
Reserved
R
W
0x7FFF06
BDMCCRL R
W
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ENBDM
X
BDMACT
0
SDV
TRACE
CLKSW
X
UNSEC
0
Bit 7
X
6
X
5
X
4
X
3
X
2
X
1
0
Bit 0
0
X
X
X
X
X
X
= Unimplemented, Reserved
X
= Indeterminate
0
= Implemented (do not alter)
= Always read zero
Figure 7-2. BDM Register Summary
MC9S12XE-Family Reference Manual , Rev. 1.19
280
Freescale Semiconductor