S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 1 Device Overview MC9S12XE-Family
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1.1.2
Modes of Operation
Memory map and bus interface modes:
• Normal and emulation operating modes
— Normal single-chip mode
— Normal expanded mode
— Emulation of single-chip mode
— Emulation of expanded mode
• Special Operating Modes
— Special single-chip mode with active background debug mode
— Special test mode (Freescale
use only)
Low-power modes:
• System stop modes
— Pseudo stop mode
— Full stop mode with fast wake-up option
• System wait mode
Operating system states
• Supervisor state
• User state
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
31
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Low-power wake-up timer (API)
— Available in all modes including Full Stop Mode
— Trimmable to +-5% accuracy
— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
Input/Output
— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins
— Hysteresis and configurable pull up/pull down device on all input pins
— Configurable drive strength on all output pins
Package Options
— 208-pin MAPBGA
— 144-pin low-profile quad flat-pack (LQFP)
— 112-pin low-profile quad flat-pack (LQFP)
— 80-pin quad flat-pack (QFP)
50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency
