S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
Table 2-88. PTL Register Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
7
PTL
Description
Port L general purpose input/output data—Data
Register
Port L pin 7 is associated with the TXD signal of the SCI7 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 6 is associated with the RXD signal of the SCI7 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 2 is associated with the RXD signal of the SCI5 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data
Register
Port L pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTL
5
PTL
4
PTL
3
PTL
2
PTL
1
PTL
0
PTL
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
169
