S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
Table 2-87. PTR Routing Register Field Descriptions (continued)
Field
5
PTRRR
Description
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC5 is available on PP5
0 TIMIOC5 is available on PR5
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC4 is available on PP4
0 TIMIOC4 is available on PR4
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC3 is available on PP3
0 TIMIOC3 is available on PR3
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC2 is available on PP2
0 TIMIOC2 is available on PR2
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC1 is available on PP1
0 TIMIOC1 is available on PR1
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC0 is available on PP0
0 TIMIOC0 is available on PR0
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
4
PTRRR
3
PTRRR
2
PTRRR
1
PTRRR
0
PTRRR
2.3.93
Port L Data Register (PTL)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0370
7
R
PTL7
W
Altern.
Function
Reset
(TXD7)
0
(RXD7)
0
(TXD6)
0
(RXD6)
0
(TXD5)
0
(RXD5)
0
(TXD4)
0
(RXD4)
0
PTLT6
PTL5
PTL4
PTL3
PTL2
PTL1
PTL0
Figure 2-91. Port L Data Register (PTL)
1. Read: Anytime.
Write: Anytime.
MC9S12XE-Family Reference Manual , Rev. 1.19
168
Freescale Semiconductor
