S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Appendix A Electrical Characteristics
In
Table A-28
the timing characteristics for master mode are listed.
Table A-28. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
1
C
D
D
D
D
D
D
D
D
D
D
D
D
SCK period
Characteristic
SCK frequency
Enable lead time
Enable lag time
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid after SCK edge
Data valid after SS fall (CPHA = 0)
Data hold time (outputs)
Rise and fall time inputs
Rise and fall time outputs
Symbol
f
sck
t
sck
t
lead
t
lag
t
wsck
t
su
t
hi
t
vsck
t
vss
t
ho
t
rfi
t
rfo
Min
1/2048
2
1
Typ
—
—
1/2
1/2
1/2
—
—
—
—
—
—
—
Max
1/2
1
2048
—
—
—
—
—
15
15
—
8
8
Unit
f
bus
t
bus
t
sck
t
sck
t
sck
ns
ns
ns
ns
ns
ns
ns
—
—
—
8
8
—
—
0
—
—
See
Figure A-9.
f
SCK
/f
bus
1/2
1/4
5
10
15
20
25
30
35
40
f
bus
[MHz]
Figure A-9. Derating of maximum f
SCK
to f
bus
ratio in Master Mode
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
1243
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages