S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
Offset Module Base + 0x0005
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
7
6
5
4
3
2
1
0
R
ERSERIE
W
Reset
0
0
PGMERIE
0
EPVIOLIE
0
0
ERSVIE1
0
ERSVIE0
0
DFDIE
0
SFDIE
0
= Unimplemented or Reserved
Figure 26-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
Table 26-16. FERCNFG Field Descriptions
Field
7
ERSERIE
Description
EEE Erase Error Interrupt Enable
— The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see
Section 26.3.2.8)
EEE Program Error Interrupt Enable
— The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see
Section 26.3.2.8)
EEE Protection Violation Interrupt Enable
— The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see
Section 26.3.2.8)
EEE Error Type 1 Interrupt Enable
— The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see
Section 26.3.2.8)
EEE Error Type 0 Interrupt Enable
— The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see
Section 26.3.2.8)
Double Bit Fault Detect Interrupt Enable
— The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Section 26.3.2.8)
Single Bit Fault Detect Interrupt Enable
— The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
Section 26.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see
Section 26.3.2.8)
6
PGMERIE
4
EPVIOLIE
3
ERSVIE1
2
ERSVIE0
1
DFDIE
0
SFDIE
26.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
MC9S12XE-Family Reference Manual , Rev. 1.19
970
Freescale Semiconductor
