S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-2. External System Signals Associated with XEBI
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
EBI Signal
Multiplex
(T)ime
(2)
(F)unction
(3)
—
T
—
—
—
T
—
—
T
—
—
T
F
Available in Modes
Description
NS
Read Enable, indicates external read access
External address
Access source
External address
Instruction Queue Status
External address
Internal visibility read data
External address
Internal visibility read data
—
—
—
—
—
—
—
—
—
—
—
—
—
F
F
Upper Data Select, indicates external access
to the high byte DATA[15:8]
Low Strobe, indicates valid data on DATA[7:0]
Lower Data Select, indicates external access
to the low byte DATA[7:0]
Read/Write, indicates the direction of internal
data transfers
Write Enable, indicates external write access
Chip select
Bidirectional data (even address)
Bidirectional data (odd address)
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
NX
Yes
Yes
No
Yes
No
Yes
No
No
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
ES
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
No
Yes
Yes
EX
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
ST
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Signal
I
(1)
/O
RE
ADDR[22:20]
ACC[2:0]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:1]
IVD[15:1]
ADDR0
IVD0
UDS
LSTRB
LDS
RW
WE
CS[3:0]
DATA[15:8]
DATA[7:0]
EWAIT
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I
External control for external bus access
No No Yes No Yes No
stretches (adding wait states)
1. All inputs are capable of reducing input threshold level
2. Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
time slot (in modes where applicable).
3. Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
depending on configuration and reset state.
MC9S12XE-Family Reference Manual , Rev. 1.19
244
Freescale Semiconductor
