S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
10.8.1.3
Immediate 3-Bit Wide (IMM3)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Operands for immediate mode instructions are included in the instruction stream and are fetched into the
instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an
immediate addressing mode operand. This address mode is used for semaphore instructions.
Examples:
CSEM
SSEM
#1
#3
; Unlock semaphore 1
; Lock Semaphore 3
10.8.1.4
Immediate 4 Bit Wide (IMM4)
The 4 bit wide immediate addressing mode is supported by all shift instructions.
RD = RD
∗
IMM4
Examples:
LSL
LSR
R4,#1
R4,#3
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
10.8.1.5
Immediate 8 Bit Wide (IMM8)
The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP).
RD = RD
∗
imm8
Examples:
ADDL
SUBL
LDH
CMPL
R1,#1
R2,#2
R3,#3
R4,#4
;
;
;
;
adds an 8 bit value to register R1
subtracts an 8 bit value from register R2
loads an 8 bit immediate into the high byte of Register R3
compares the low byte of register R4 with an immediate value
10.8.1.6
Immediate 16 Bit Wide (IMM16)
The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which
offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode.
RD = RD
∗
IMM16
Examples:
LDW
ADD
R4,#$1234
R4,#$5678
; translated to LDL R4,#$34; LDH R4,#$12
; translated to ADDL R4,#$78; ADDH R4,#$56
10.8.1.7
Monadic Addressing (MON)
In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)),
the target (RD =
f()),
or both source and target of the operation (RD =
f(RD)).
Examples:
JAL
SIF
R1
R2
; PC = R1, R1 = PC+2
; Trigger IRQ associated with the channel number in R2.L
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
381
