S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
10.3.1.18 XGATE Register 6 (XGR6)
Module Base +0x0002C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
XGR6
0
0
0
0
0
0
0
0
Figure 10-20. XGATE Register 6 (XGR6)
Read: In debug mode if unsecured and not idle (XGCHID
≠
0x00)
Write: In debug mode if unsecured and not idle (XGCHID
≠
0x00)
Table 10-20. XGR6 Field Descriptions
Field
15–0
XGR6[15:0]
Description
XGATE Register 6
— The RISC core’s register 6
10.3.1.19 XGATE Register 7 (XGR7)
The XGR7 register (Figure
10-21)
provides access to the RISC core’s register 7.
Module Base +0x0002E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
XGR7
0
0
0
0
0
0
0
0
Figure 10-21. XGATE Register 7 (XGR7)
Read: In debug mode if unsecured and not idle (XGCHID
≠
0x00)
Write: In debug mode if unsecured and not idle (XGCHID
≠
0x00)
Table 10-21. XGR7 Field Descriptions
Field
15–0
XGR7[15:0]
Description
XGATE Register 7
— The RISC core’s register 7
10.4
Functional Description
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories
and peripherals (see
Figure 10-1).
The RISC processor always remains in an idle state until it is triggered
by an XGATE request. Then it executes a code sequence (thread) that is associated with the requested
XGATE channel. Each thread can run on a priority level ranging from 1 to 7. Refer to the
S12X_INT
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
371
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
The XGR6 register (Figure
10-20)
provides access to the RISC core’s register 6.
