S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 3 Memory Mapping Control (S12XMMCV4)
3.1.3
S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-
bit address load/store instructions.
• a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be
considered as the local map accessed by the 16-bit (CPU or BDM) address.
• The XGATE 64 Kbyte local map.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1
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Power Saving Modes
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
3.1.4.2
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Functional Modes
Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
1. Resources are also called targets.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
189
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
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Simultaneous accesses to different resources
1
(internal, external, and peripherals) (see
Figure 3-1
)
Resolution of target bus access collision
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
