S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
26.4.2
Flash Command Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see
Section 26.3.2.7).
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
26.4.2.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 26-33. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
0x01
FCCOB Parameters
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 26-34. Erase Verify All Blocks Command Error Handling
Register
Error Bit
ACCERR
Set if a Load Data Field command sequence is currently active
FSTAT
FPVIOL
MGSTAT1
MGSTAT0
None
Set if any errors have been encountered during the read
(1)
Set if any non-correctable errors have been encountered during the read
1
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
FERSTAT
EPVIOLIF
None
1. As found in the memory map for FTM512K3.
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
989
