S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Figure 16-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
= Unused, always read ‘x’
Read: For transmit buffers, anytime when TXEx flag is set (see
Section 16.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”)
and the corresponding transmit buffer is selected in CANTBSEL (see
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).
Write: For transmit buffers, anytime when TXEx flag is set (see
Flag Register (CANTFLG)”)
and the corresponding transmit buffer is selected in CANTBSEL (see
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Reset: Undefined (0x00XX) because of RAM-based implementation
Figure 16-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
IDR0
0x00X0
R
ID10
W
R
ID2
W
R
W
R
W
ID1
ID0
RTR
IDE (=0)
ID9
ID8
ID7
ID6
ID5
ID4
ID3
Bit 7
6
5
4
3
2
1
Bit 0
IDR1
0x00X1
IDR2
0x00X2
IDR3
0x00X3
= Unused, always read ‘x’
16.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
MC9S12XE-Family Reference Manual , Rev. 1.19
632
Freescale Semiconductor
