S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read or write: Anytime
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
All bits reset to zero.
The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register.
Table 14-13. TIE Field Descriptions
Field
7:0
C[7:0]I
Description
Input Capture/Output Compare “x” Interrupt Enable
0 The corresponding flag is disabled from causing a hardware interrupt.
1 The corresponding flag is enabled to cause an interrupt.
14.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
W
Reset
TOI
0
0
0
0
0
0
0
TCRE
0
PR2
0
PR1
0
PR0
0
= Unimplemented or Reserved
Figure 14-16. Timer System Control Register 2 (TSCR2)
Read or write: Anytime
All bits reset to zero.
Table 14-14. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
Description
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable
— This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note:
If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select
— These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See
Table 14-15.
2:0
PR[2:0]
Table 14-15. Prescaler Selection
PR2
0
0
0
PR1
0
0
1
PR0
0
1
0
Prescale Factor
1
2
4
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
539
