S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 7 Background Debug Module (S12XBDMV2)
7.4.3
BDM Hardware Commands
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU on the
SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control
registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in
Table 7-6.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
Table 7-6. Hardware Commands
Command
BACKGROUND
ACK_ENABLE
ACK_DISABLE
READ_BD_BYTE
READ_BD_WORD
READ_BYTE
READ_WORD
WRITE_BD_BYTE
WRITE_BD_WORD
WRITE_BYTE
Opcode
(hex)
90
D5
D6
E4
EC
E0
E8
C4
CC
C0
Data
None
None
None
Description
Enter background mode if firmware is enabled. If enabled, an ACK will be
issued when the part enters active background mode.
Enable Handshake. Issues an ACK pulse after the command is executed.
Disable Handshake. This command does not issue an ACK pulse.
16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Odd address data on low byte; even address data on high byte.
16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Must be aligned access.
16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Odd address data on low byte; even address data on high byte.
16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Must be aligned access.
16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Odd address data on low byte; even address data on high byte.
16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Must be aligned access.
16-bit address Write to memory with standard BDM firmware lookup table out of map.
16-bit data in Odd address data on low byte; even address data on high byte.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
287
