S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Table 11-6. CLKSEL Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
7
PLLSEL
Description
PLL Select Bit
Write: Anytime.
Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as
SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
0 System clocks are derived from OSCCLK (f
BUS
= f
OSC
/ 2).
1 System clocks are derived from PLLCLK (f
BUS
= f
PLL
/ 2).
Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop).
Note:
Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Oscillator Configuration Status Bit
— This read-only bit shows the oscillator configuration status.
0 Loop controlled Pierce Oscillator is selected.
1 External clock / full swing Pierce Oscillator is selected.
PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains
set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set
manually if PLL clock is required.
0 IPLL keeps running in Wait Mode.
1 IPLL stops in Wait Mode.
RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in Wait Mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.
COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in Wait Mode.
1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.
6
PSTP
5
XCLKS
3
PLLWAI
1
RTIWAI
0
COPWAI
11.3.2.7
S12XECRG IPLL Control Register (PLLCTL)
This register controls the IPLL functionality.
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
CME
W
Reset
1
1
0
0
0
0
0
1
PLLON
FM1
FM0
FSTWKP
PRE
PCE
SCME
Figure 11-9. S12XECRG IPLL Control Register (PLLCTL)
MC9S12XE-Family Reference Manual , Rev. 1.19
476
Freescale Semiconductor
