S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
2.3.61
Port J Data Register (PTJ)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0268
7
R
PTJ7
W
Altern.
Function
TXCAN4
SCL0
(TXCAN0)
Reset
0
RXCAN4
SDA0
(RXCAN0)
0
—
SCL1
CS2
0
—
SDA1
CS0
0
—
—
—
0
—
—
CS1
0
TXD2
—
—
0
RXD2
—
CS3
0
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
Figure 2-59. Port J Data Register (PTJ)
1. Read: Anytime.
Write: Anytime.
Table 2-57. PTJ Register Field Descriptions
Field
7-6
PTJ
Description
Port J general purpose input/output data—Data
Register
Port J pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN4 and the routed CAN0, as well as with
SCL and SDA signals of IIC0, respectively.
The CAN4 function takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the
CAN4 module is enabled. The IIC0 function takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as
open drain outputs. The routed CAN0 function takes precedence over the general purpose I/O function if the routed
CAN0 module is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data
Register
This pin is associated with the SCL and SDA signals of IIC1, and with chip select outputs CS2 and CS0, respectivley.
The IIC1 function takes precedence over the chip select and general purpose I/O function if the IIC1 is enabled. The
chip selects take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1
outputs are configured as open drain outputs. Refer to IIC section for details.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data
Register
This pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data
Register
This pin is associated with the chip select output signal CS2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5-4
PTJ
3
PTJ
2
PTJ
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
149
