S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 4 Memory Protection Unit (S12XMPUV1)
Table 4-9. MPUDESC1 Field Descriptions
Field
Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Memory range lower boundary address bits
— The LOW_ADDR[18:11] bits represent bits [18:11] of the
7–0
LOW_ADDR[ global memory address that is used as the lower boundary for the described memory range.
18:11]
4.3.1.8
MPU Descriptor Register 2 (MPUDESC2)
7
6
5
4
3
2
1
0
Address: Module Base + 0x0008
R
W
Reset
0
0
0
LOW_ADDR[10:3]
0
0
0
0
0
Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)
Read: Anytime
Write: Anytime
Table 4-10. MPUDESC2 Field Descriptions
Field
Description
7–0
Memory range lower boundary address bits
— The LOW_ADDR[10:3] bits represent bits [10:3] of the global
LOW_ADDR[ memory address that is used as the lower boundary for the described memory range.
10:3]
4.3.1.9
MPU Descriptor Register 3 (MPUDESC3)
7
6
5
4
3
2
1
0
Address: Module Base + 0x0009
R
W
Reset
0
0
0
0
1
WP
0
NEX
0
HIGH_ADDR[22:19]
1
1
1
Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)
Read: Anytime
Write: Anytime
Table 4-11. MPUDESC3 Field Descriptions
Field
7
WP
Description
Write-Protect bit
— The WP bit causes the described memory range to be treated as write-protected. If this
bit is set every attempt to write in the described memory range causes an access violation.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
235
