S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-7. EBICTL1 Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
Description
6–4
External Access Stretch Option 1 Bits 2, 1, 0
— This three bit field determines the amount of additional clock
EXSTR1[2:0] stretch cycles on every access to the external address space as shown in
Table 5-8.
2–0
External Access Stretch Option 0 Bits 2, 1, 0
— This three bit field determines the amount of additional clock
EXSTR0[2:0] stretch cycles on every access to the external address space as shown in
Table 5-8. External Access Stretch Bit Definition
EXSTRx[2:0]
000
001
010
011
100
101
110
111
Number of Stretch Cycles
1
2
3
4
5
6
7
8
5.4
Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
5.4.1
Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in
Table 5-9.
Table 5-9. Summary of Functions
Single-Chip Modes
Properties
(if Enabled)
Normal
Single-Chip
Special
Single-Chip
Normal
Expanded
Expanded Modes
Emulation
Single-Chip
Emulation
Expanded
Special
Test
Timing Properties
PRR access
(1)
2 cycles
read internal
write internal
—
—
2 cycles
read internal
write internal
—
—
2 cycles
read internal
write internal
—
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
(3)
2 cycles
read external
write int & ext
1 cycle
1 cycle
2 cycles
read external
write int & ext
1 cycle
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
3
2 cycles
read internal
write internal
1 cycle
1 cycle
Internal access
visible externally
External
address access
and
unimplemented area
access
(2)
MC9S12XE-Family Reference Manual , Rev. 1.19
248
Freescale Semiconductor
