S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
2.3.59
Read: Anytime.
Port H Interrupt Enable Register (PIEH)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0266
7
R
PIEH7
W
Reset
0
0
0
0
0
0
0
0
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
Figure 2-57. Port H Interrupt Enable Register (PIEH)
1. Read: Anytime.
Write: Anytime.
Table 2-55. PPSP Register Field Descriptions
Field
7-0
PIEH
Description
Port H interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.60
Port H Interrupt Flag Register (PIFH)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0267
7
R
PIFH7
W
Reset
0
0
0
0
0
0
0
0
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
Figure 2-58. Port H Interrupt Flag Register (PIFH)
1. Read: Anytime.
Write: Anytime.
Table 2-56. PPSP Register Field Descriptions
Field
7-0
PIFH
Description
Port H interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
MC9S12XE-Family Reference Manual , Rev. 1.19
148
Freescale Semiconductor
