S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Table 13-4. ATDCTL1 Field Descriptions (continued)
Field
4
SMP_DIS
Description
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
3–0
External Trigger Channel Select
— These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in
Table 13-6.
Table 13-5. A/D Resolution Coding
SRES1
0
0
1
1
SRES0
0
1
0
1
A/D Resolution
8-bit data
10-bit data
12-bit data
Reserved
Table 13-6. External Trigger Channel Select Coding
ETRIGSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
ETRIGCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
ETRIGCH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
ETRIGCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
ETRIGCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
External trigger source is
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ETRIG0
(1)
ETRIG1
1
ETRIG2
1
ETRIG3
1
Reserved
1
1
X
X
X
Reserved
1. Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
MC9S12XE-Family Reference Manual , Rev. 1.19
508
Freescale Semiconductor
