S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Module Base + 0x0022
7
6
5
4
3
2
1
0
R
W
Reset
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
0
0
0
0
0
0
PACNT1(9)
0
PACNT0(8)
0
Figure 14-37. Pulse Accumulators Count Register 3 (PACN3)
Module Base + 0x0023
7
6
5
4
3
2
1
0
R
W
Reset
PACNT7
0
PACNT6
0
PACNT5
0
PACNT4
0
PACNT3
0
PACNT2
0
PACNT1
0
PACNT0
0
Figure 14-38. Pulse Accumulators Count Register 2 (PACN2)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
14.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Module Base + 0x0024
7
6
5
4
3
2
1
0
R
W
Reset
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
0
0
0
0
0
0
PACNT1(9)
0
PACNT0(8)
0
Figure 14-39. Pulse Accumulators Count Register 1 (PACN1)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
547
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
