S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Figure 11-22
and
Figure 11-23
show the power-up sequence for cases when the RESET pin is tied to V
DD
and when the RESET pin is held low.
Clock Quality Check
(no Self-Clock Mode)
)(
RESET
Internal POR
)(
128 SYSCLK
Internal RESET
)(
64 SYSCLK
Figure 11-22. RESET Pin Tied to V
DD
(by a Pull-up Resistor)
RESET
Clock Quality Check
(no Self Clock Mode)
)(
Internal POR
)(
128 SYSCLK
Internal RESET
)(
64 SYSCLK
Figure 11-23. RESET Pin Held Low Externally
11.6
Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in
Table 11-18.
Refer to MCU
specification for related vector addresses and priorities.
Table 11-18. S12XECRG Interrupt Vectors
Interrupt Source
Real time interrupt
LOCK interrupt
SCM interrupt
CCR
Mask
I bit
I bit
I bit
Local Enable
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
495
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
