S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
Table 10-2. XGMCTL Field Descriptions (Sheet 2 of 3)
Field
11
XGFACTM
Description
XGFACT Mask
— This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or
cleared if a "1" is written to the XGFACTM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGFACT in the same bus cycle
1 Enable write access to the XGFACT in the same bus cycle
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
9
XGSWEF Mask
— This bit controls the write access to the XGSWEF bit. The XGSWEF bit can only be cleared
XGSWEFM if a "1" is written to the XGSWEFM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGSWEF in the same bus cycle
1 Enable write access to the XGSWEF in the same bus cycle
8
XGIEM
XGIE Mask
— This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1"
is written to the XGIEM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGIE in the same bus cycle
1 Enable write access to the XGIE in the same bus cycle
XGATE Module Enable (Request Enable)—
This bit enables incoming XGATE requests from the S12X_INT
module. If the XGE bit is cleared, pending XGATE requests will be ignored. The thread that is executed by the
RISC core while the XGE bit is cleared will continue to run.
Read:
0 Incoming requests are disabled
1 Incoming requests are enabled
Write:
0 Disable incoming requests
1 Enable incoming requests
Halt XGATE in Freeze Mode
— The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active).
Read:
0 RISC core operates normally in Freeze (BDM active)
1 RISC core stops in Freeze Mode (BDM active)
Write:
0 Don’t stop RISC core in Freeze Mode (BDM active)
1 Stop RISC core in Freeze Mode (BDM active)
XGATE Debug Mode
— This bit indicates that the XGATE is in Debug Mode (see
Section 10.6, “Debug Mode”).
Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see
S12X_DBG Section),
or by writing a "1" to this bit.
Read:
0 RISC core is not in Debug Mode
1 RISC core is in Debug Mode
Write:
0 Leave Debug Mode
1 Enter Debug Mode
Note:
Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
7
XGE
6
XGFRZ
5
XGDBG
MC9S12XE-Family Reference Manual , Rev. 1.19
358
Freescale Semiconductor
