S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 5 External Bus Interface (S12XEBIV4)
Refer to the S12X_MMC section for a detailed description of the MCU operating modes.
5.1.4
Block Diagram
Figure 5-1
is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0]
DATA[15:0]
IVD[15:0]
LSTRB
RW
EWAIT
XEBI
UDS
LDS
RE
WE
ACC[2:0]
IQSTAT[3:0]
CS[3:0]
Figure 5-1. XEBI Block Diagram
5.2
External Signal Description
NOTE
The following external bus related signals are described in other sections:
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
Table 5-2
outlines the pin names and gives a brief description of their function. Refer to the SoC section
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
243
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages