S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 22 Timer Module (TIM16B8CV2) Block Description
22.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
C7F
W
Reset
0
0
0
0
0
0
0
0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
Figure 22-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 22-15. TRLG1 Field Descriptions
Field
7:0
C[7:0]F
Description
Input Capture/Output Compare Channel “x” Flag
— These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
22.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
TOF
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 22-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
MC9S12XE-Family Reference Manual , Rev. 1.19
802
Freescale Semiconductor
