S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.2
Timer Compare Force Register (CFORC)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
W
Reset
0
FOC7
0
0
FOC6
0
0
FOC5
0
0
FOC4
0
0
FOC3
0
0
FOC2
0
0
FOC1
0
0
FOC0
0
Figure 14-4. Timer Compare Force Register (CFORC)
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
Table 14-3. CFORC Field Descriptions
Field
7:0
FOC[7:0]
Description
Force Output Compare Action for Channel 7:0
— A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note:
A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare
on any channel occurs at the same time as the successful output compare, then the forced output compare
action will take precedence and the interrupt flag will not get set.
14.3.2.3
Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
W
Reset
OC7M7
0
OC7M6
0
OC7M5
0
OC7M4
0
OC7M3
0
OC7M2
0
OC7M1
0
OC7M0
0
Figure 14-5. Output Compare 7 Mask Register (OC7M)
Read or write: Anytime
All bits reset to zero.
Table 14-4. OC7M Field Descriptions
Field
7:0
OC7M[7:0]
Description
Output Compare Mask Action for Channel 7:0
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a successful channel 7 output compare, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
successful channel 7 output compare.
Note:
The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred
from the output compare 7 data register to the timer port.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
533
