S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Data A Received
Data B Received
Data C Received
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
SPIF Serviced
Receive Shift Register
Data A
Data B
Data C
SPIF
SPI Data Register
Data A
Data B
Data C
= Unspecified
= Reception in progress
Figure 21-9. Reception with SPIF serviced in Time
Data A Received
Data B Received
Data C Received
Data B Lost
SPIF Serviced
Receive Shift Register
Data A
Data B
Data C
SPIF
SPI Data Register
Data A
Data C
= Unspecified
= Reception in progress
Figure 21-10. Reception with SPIF serviced too late
21.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,
the four associated SPI port pins are dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
773