S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 4 Memory Protection Unit (S12XMPUV1)
4.3.1.4
MPU Address Status Register 2 (MPUASTAT2)
7
6
5
4
3
2
1
0
Address: Module Base + 0x0003
R
W
Reset
0
0
0
0
0
0
0
0
ADDR[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Figure 4-6. MPU Address Status Register (MPUASTAT2)
Read: Anytime
Write: Never
Table 4-6. MPUASTAT2 Field Descriptions
Field
7–0
ADDR[7:0]
Description
Access violation address bits
— The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
4.3.1.5
MPU Descriptor Select Register (MPUSEL)
7
6
5
4
3
2
1
0
Address: Module Base + 0x0005
R
W
Reset
0
0
0
0
0
0
0
0
0
SVSEN
0
SEL[2:0]
0
0
Figure 4-7. MPU Descriptor Select Register (MPUSEL)
Read: Anytime
Write: Anytime
Table 4-7. MPUSEL Field Descriptions
Field
7
SVSEN
Description
MPU supervisor state enable bit
— This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
Descriptor select bits
— The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5).
2–0
SEL[2:0]
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
233
