S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 3 Memory Mapping Control (S12XMMCV4)
3.4.3
Chip Access Restrictions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of
access violation, the suspect master is acknowledged with an indication of an error; the victim target will
not be accessed.
Other violations MPU is not handling are listed below.
3.4.3.1
Illegal XGATE Accesses
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
• XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
• XGATE accesses the register space (in case of opcode or vector fetch).
• XGATE performs a write to Flash in any modes (in case of load-store access).
• XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
For further details refer to the XGATE Block Guide.
3.4.4
Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 3-23
1
).
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
217
