S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 3 Memory Mapping Control (S12XMMCV4)
BDM HARDWARE COMMAND
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Global Address [22:0]
Bit22
Bit16 Bit15
Bit0
BDMGPR Register [6:0]
BDM Local Address
BDM FIRMWARE COMMAND
Global Address [22:0]
Bit22
Bit16 Bit15
Bit0
BDMGPR Register [6:0]
CPU Local Address
Figure 3-18. BDMGPR Address Mapping
3.4.2.3
Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, EEE, and FLASH) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the Device User Guide for further details.
Figure 3-19
and
Table 3-17
show the memory spaces occupied by the on-chip resources. Please note that
the memory spaces have fixed top addresses.
Table 3-17. Global Implemented Memory Space
Internal Resource
RAM
$Address
RAM_LOW = 0x10_0000 minus RAMSIZE
(1)
FLASH
FLASH_LOW = 0x80_0000 minus FLASHSIZE
(2)
1. RAMSIZE is the hexadecimal value of RAM SIZE in bytes
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
When the device is operating in expanded modes except emulation single-chip mode, accesses to global
addresses which are not occupied by the on-chip resources (unimplemented areas or external memory
space) result in accesses to the external bus (see
Figure 3-19).
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
209
