S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Table 19-3. Clock A Prescaler Selects (continued)
PCKA2
1
PCKA1
1
PCKA0
1
Value of Clock A
Bus clock / 128
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
19.3.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 19.4.2.5, “Left Aligned Outputs”
and
Section 19.4.2.6, “Center Aligned Outputs”
for a more
detailed description of the PWM output modes.
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
W
Reset
CAE7
0
CAE6
0
CAE5
0
CAE4
0
CAE3
0
CAE2
0
CAE1
0
CAE0
0
Figure 19-7. PWM Center Align Enable Register (PWMCAE)
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Field
7–0
CAE[7:0]
Description
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
19.3.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
W
Reset
CON67
0
CON45
0
CON23
0
CON01
0
PSWAI
0
PFRZ
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-8. PWM Control Register (PWMCTL)
Read: Anytime
Write: Anytime
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
701
