S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Table 21-4. SPICR2 Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
6
XFRW
Description
Transfer Width —
This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to
Section 21.3.2.4, “SPI Status Register (SPISR)
for
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)
(1)
1 16-bit Transfer Width (n = 16)
1
Mode Fault Enable Bit
— This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to
Table 21-3.
In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation
— This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
SPI Stop in Wait Mode Bit
— This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
4
MODFEN
3
BIDIROE
1
SPISWAI
0
Serial Pin Control Bit 0
— This bit enables bidirectional pin configurations as shown in
Table 21-5.
In master
SPC0
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
1. n is used later in this document as a placeholder for the selected transfer width.
Table 21-5. Bidirectional Pin Configurations
Pin Mode
SPC0
BIDIROE
MISO
MOSI
Master Mode of Operation
Normal
Bidirectional
0
1
X
0
1
Slave Mode of Operation
Normal
Bidirectional
0
1
X
0
1
Slave Out
Slave In
Slave I/O
Slave In
MOSI not used by SPI
Master In
MISO not used by SPI
Master Out
Master In
Master I/O
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
767
